11 search results - page 2 / 3 » A Formal Semantics of Clock Refinement in Imperative Synchro... |
CHARME
2001
Springer
13 years 9 months ago
2001
Springer
We describe SAFL+: a call-by-value, parallel language in the style of ML which combines imperative, concurrent and functional programming. Synchronous channels allow communication ...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors...
ENTCS
2006
13 years 4 months ago
2006
Latency insensitive protocols (LIPs) have been proposed as a viable means to connect synchronous IP blocks via long interconnects in a system-on-chip. The reason why one needs to ...
EMSOFT
2007
Springer
13 years 11 months ago
2007
Springer
We explain the design of the interpretation-based static analyzer Astr´ee and its use to prove the absence of run-time errors in safety-critical codes. Categories and Subject Des...
FDL
2004
IEEE
13 years 8 months ago
2004
IEEE
System-on-Chip (SOC) and other complex distributed hardware/software systems contain heterogeneous components such as DSPs, micro-controllers, application specific logic etc., whi...