35 search results - page 2 / 7 » A Framework for Interprocedural Locality Optimization Using ... |
TJS
2002
13 years 4 months ago
2002
A significant source for enhancing application performance and for reducing power consumption in embedded processor applications is to improve the usage of the memory hierarchy. In...
VLSID
2002
IEEE
13 years 9 months ago
2002
IEEE
This paper introduces a dynamic layout optimization strategy to minimize the number of cycles spent in memory accesses in a cache-based memory environment. In this approach, a giv...
IEEEPACT
2009
IEEE
13 years 11 months ago
2009
IEEE
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
SC
1995
ACM
13 years 8 months ago
1995
ACM
This paper presents an extensive empirical evaluation of an interprocedural parallelizing compiler, developed as part of the Stanford SUIF compiler system. The system incorporates...
IEEEPACT
2009
IEEE
13 years 2 months ago
2009
IEEE
As the gap between processor and memory continues to grow, memory performance becomes a key performance bottleneck for many applications. Compilers therefore increasingly seek to m...