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» A Framework for Scheduler Synthesis
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DAC
1999
ACM
14 years 5 months ago
Soft Scheduling in High Level Synthesis
In this paper, we establish a theoretical framework for a new concept of scheduling called soft scheduling. In contrasts to the traditional schedulers referred as hard schedulers,...
Jianwen Zhu, Daniel Gajski
RTSS
1999
IEEE
13 years 8 months ago
A Framework for Scheduler Synthesis
In this paper we present a framework integrating speci cation and scheduler generation for real-time systems. In a rst step, the system, which can include arbitrarily designed tas...
Karine Altisen, Gregor Gößler, Amir Pnu...
VLSID
2003
IEEE
134views VLSI» more  VLSID 2003»
14 years 4 months ago
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis
Abstract-- In battery driven portable applications, the minimization of energy, average power, peak power, and peak power differential are equally important to improve reliability ...
Saraju P. Mohanty, N. Ranganathan
DATE
2008
IEEE
116views Hardware» more  DATE 2008»
13 years 10 months ago
A Variation Aware High Level Synthesis Framework
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
Feng Wang 0004, Guangyu Sun, Yuan Xie
DATE
2009
IEEE
125views Hardware» more  DATE 2009»
13 years 11 months ago
HLS-l: High-level synthesis of high performance latch-based circuits
An inherent performance gap between custom designs and ASICs is one of the reasons why many designers still start their designs from register transfer level (RTL) description rath...
Seungwhun Paik, Insup Shin, Youngsoo Shin