23 search results - page 5 / 5 » A Framework for the Validation of Processor Architecture Com... |
ICS
2009
Tsinghua U.
14 years 1 days ago
2009
Tsinghua U.
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
MICRO
2007
IEEE
13 years 11 months ago
2007
IEEE
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
DAC
2003
ACM
14 years 6 months ago
2003
ACM
A binary decoder is a common component of software development tools such as instruction set simulators, disassemblers and debuggers. The efficiency of the decoder can have a sign...