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DSD
2002
IEEE
102views Hardware» more  DSD 2002»
13 years 10 months ago
Formal Verification of a DSP Chip Using an Iterative Approach
In this paper we describe a methodology for the formal verification of a DSP chip using the HOL theorem prover. We used an iterative method to specify both the behavioral and stru...
Ali Habibi, Sofiène Tahar, Adel Ghazel
VLSID
2002
IEEE
189views VLSI» more  VLSID 2002»
14 years 5 months ago
Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...
Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, ...
BMCBI
2010
178views more  BMCBI 2010»
13 years 5 months ago
Applications of a formal approach to decipher discrete genetic networks
Background: A growing demand for tools to assist the building and analysis of biological networks exists in systems biology. We argue that the use of a formal approach is relevant...
Fabien Corblin, Eric Fanchon, Laurent Trilling
FM
2008
Springer
77views Formal Methods» more  FM 2008»
13 years 7 months ago
A Rigorous Approach to Networking: TCP, from Implementation to Protocol to Service
Abstract. Despite more then 30 years of research on protocol specification, the major protocols deployed in the Internet, such as TCP, are described only in informal prose RFCs and...
Tom Ridge, Michael Norrish, Peter Sewell
ENTCS
2008
83views more  ENTCS 2008»
13 years 5 months ago
Elastic Flow in an Application Specific Network-on-Chip
A Network-on-Chip (NoC) is increasingly needed to interconnect the large number and variety of Intellectual Property (IP) cells that make up a System-on-Chip (SoC). The network mu...
Daniel Gebhardt, Kenneth S. Stevens