2 search results - page 1 / 1 » A Generic Architecture for On-Chip Packet-Switched Interconn... |
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today's dominant template, will not me...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...