29 search results - page 1 / 6 » A Graph Based Framework to Detect Optimal Memory Layouts for... |
IPPS
1999
IEEE
13 years 8 months ago
1999
IEEE
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
ICPP
1999
IEEE
13 years 8 months ago
1999
IEEE
There has been much work recently on improving the locality performance of loop nests in scientific programs through the use of loop as well as data layout optimizations. However,...
EUC
2006
Springer
13 years 8 months ago
2006
Springer
As the ever-increasing gap between the speed of processor and the speed of memory has become the cause of one of primary bottlenecks of computer systems, modern architecture system...
VLSID
2002
IEEE
13 years 9 months ago
2002
IEEE
This paper introduces a dynamic layout optimization strategy to minimize the number of cycles spent in memory accesses in a cache-based memory environment. In this approach, a giv...
EUROPAR
1998
Springer
13 years 8 months ago
1998
Springer
This paper aims to improve locality of references by suitably choosing array layouts. We use a new definition of spatial reuse vectors that takes into account memory layout of arra...