Sciweavers

26 search results - page 2 / 6
» A Hardware Algorithm for High Speed Morpheme Extraction and ...
Sort
View
INFOCOM
1995
IEEE
13 years 9 months ago
A Fast Bypass Algorithm for High-Speed Networks
In this work we suggest an algorithm that increases the reservation success probability for bursty tra c in high speed networks by adding exibility to the construction of the rout...
Israel Cidon, Raphael Rom, Yuval Shavitt
ICIP
2002
IEEE
14 years 8 months ago
A window-based color quantization technique and its embedded implementation
A new color quantization (CQ) technique and its VLSI implementation is introduced. It is based on image split into windows and uses Kohonen Self Organized Neural Network Classifie...
Antonios Atsalakis, Nikos Papamarkos, Dimitrios So...
ISCAS
2003
IEEE
126views Hardware» more  ISCAS 2003»
13 years 11 months ago
High-speed processor for quantum-computing emulation and its applications
A high-speed and large-scale processor dedicated to quantum computing is proposed, which has the minimum operation function needed for execution of a quantum algorithm. In this pr...
Minoru Fujishima, Kaoru Saito, M. Onouchi, Koichir...
GECCO
2007
Springer
207views Optimization» more  GECCO 2007»
14 years 14 days ago
A data parallel approach to genetic programming using programmable graphics hardware
In recent years the computing power of graphics cards has increased significantly. Indeed, the growth in the computing power of these graphics cards is now several orders of magn...
Darren M. Chitty
ISLPED
2010
ACM
206views Hardware» more  ISLPED 2010»
13 years 6 months ago
Energy efficient implementation of parallel CMOS multipliers with improved compressors
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija