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GECCO
2006
Springer
195views Optimization» more  GECCO 2006»
13 years 9 months ago
Studying XCS/BOA learning in Boolean functions: structure encoding and random Boolean functions
Recently, studies with the XCS classifier system on Boolean functions have shown that in certain types of functions simple crossover operators can lead to disruption and, conseque...
Martin V. Butz, Martin Pelikan
GECCO
2006
Springer
155views Optimization» more  GECCO 2006»
13 years 9 months ago
Comparison of genetic representation schemes for scheduling soft real-time parallel applications
This paper presents a hybrid technique that combines List Scheduling (LS) with Genetic Algorithms (GA) for constructing non-preemptive schedules for soft real-time parallel applic...
Yoginder S. Dandass, Amit C. Bugde
ICCD
1999
IEEE
110views Hardware» more  ICCD 1999»
13 years 10 months ago
TriMedia CPU64 Architecture
We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a...
Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-J...
ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
13 years 5 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
ICS
2005
Tsinghua U.
13 years 11 months ago
A NUCA substrate for flexible CMP cache sharing
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhan...