2 search results - page 1 / 1 » A High-Performance 64-bit Adder Implemented in Output Predic... |
ARVLSI
2001
IEEE
13 years 8 months ago
2001
IEEE
Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the ...
CODES
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...