8 search results - page 2 / 2 » A Hybrid ARQ Using Double Binary Turbo Codes |
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper presents a new multiprocessor platform for high throughput turbo decoding. The proposed platform is based on a new configurable ASIP combined with an efficient memory a...
RSP
2008
IEEE
13 years 11 months ago
2008
IEEE
ASIP-based implementations constitute a key trend in SoC design enabling optimal tradeoffs between performance and flexibility. This paper details a case study of an ASIP-based im...
CORR
2010
Springer
13 years 2 months ago
2010
Springer
In this paper, we show that over the binary erasure channel, Quasi-Cyclic LDPC codes can efficiently accommodate the hybrid iterative/ML decoding. We demonstrate that the quasicycl...