36 search results - page 1 / 8 » A Low Cost Fault Tolerant Packet Routing for Parallel Comput... |
IPPS
2003
IEEE
13 years 9 months ago
2003
IEEE
This work presents a new switching mechanism to tolerate arbitrary faults in interconnection networks with a negligible implementation cost. Although our routing technique can be ...
ISPA
2007
Springer
13 years 10 months ago
2007
Springer
The number of processors embedded in high performance computing platforms is growing daily to solve larger and more complex problems. The logical network topologies must also suppo...
ICPP
2000
IEEE
13 years 9 months ago
2000
IEEE
In this paper a sufficient condition is given for minimal routing in n-dimensional (n-D) meshes with faulty nodes contained in a set of disjoint fault regions. It is based on an ...
NOCS
2010
IEEE
13 years 2 months ago
2010
IEEE
Abstract--The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face...
ICDCS
2000
IEEE
13 years 9 months ago
2000
IEEE
To assure dependable onboard evolution, we have developed a methodology called guarded software upgrading (GSU). In this paper, we focus on a low-cost approach to error containmen...