4 search results - page 1 / 1 » A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micr... |
VLSID
2006
IEEE
13 years 10 months ago
2006
IEEE
As the IC process technology scales, the oxide thickness and operating voltage continues to decrease. The gate oxide thickness in recent and future IC process technology has appro...
GLVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
This paper presents the design and evaluation of a new SRAM cell made of nine transistors (9T). The proposed 9T cell utilizes a scheme with separate read and write wordlines; it i...
VLSID
2009
IEEE
14 years 5 months ago
2009
IEEE
Abstract-- Single-ended static random access memory (SESRAM) is well known for their tremendous potential of low active power and leakage dissipations. In this paper, we present a ...
TVLSI
2008
13 years 4 months ago
2008
-- Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold a...