49 search results - page 10 / 10 » A Low Power Charge-Recycling CMOS Clock Buffer |
ISVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
Powerful branch predictors along with a large branch target buffer (BTB) are employed in superscalar processors for instruction-level parallelism exploitation. However, the large ...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
: In this research, a fixed-point multimedia co-processor is designed and tested into an ARM-10 based mobile graphics processor for portable 2-D and 3-D multimedia applications. Th...
DAC
2001
ACM
14 years 5 months ago
2001
ACM
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...
EMSOFT
2007
Springer
13 years 11 months ago
2007
Springer
Design space exploration of embedded systems typically focuses on classical design goals such as cost, timing, buffer sizes, and power consumption. Robustness criteria, i.e. sensi...