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» A Memory Design in QCAs using the SQUARES Formalism
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GLVLSI
1999
IEEE
90views VLSI» more  GLVLSI 1999»
13 years 8 months ago
A Memory Design in QCAs using the SQUARES Formalism
We present a formalism for implementing circuits with Quantum-dot Cellular Automata (QCA), comprising a set of standard circuit elements with uniform layout rules. The formalism s...
Daniel Berzon, Terry J. Fountain
ISQED
2010
IEEE
126views Hardware» more  ISQED 2010»
13 years 5 months ago
Modeling and verification of industrial flash memories
We present a method to abstract, formalize, and verify industrial flash memory implementations. Flash memories contain specialized transistors, e.g., floating gate and split gate d...
Sandip Ray, Jayanta Bhadra, Thomas Portlock, Ronal...
ISLPED
1997
ACM
95views Hardware» more  ISLPED 1997»
13 years 7 months ago
Formalized methodology for data reuse exploration in hierarchical memory mappings
Efficient use of an optimized memory hierarchy to exploit temporal locality in the memory accesses on array signals can have a very large impact on the power consumption in data ...
Jean-Philippe Diguet, Sven Wuytack, Francky Cattho...
DAC
1996
ACM
13 years 7 months ago
Integrating Formal Verification Methods with A Conventional Project Design Flow
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
Ásgeir Th. Eiríksson
ICCAD
2006
IEEE
108views Hardware» more  ICCAD 2006»
14 years 15 days ago
Formal model of data reuse analysis for hierarchical memory organizations
– In real-time data-dominated communication and multimedia processing applications, due to the manipulation of large sets of data, a multi-layer memory hierarchy is used to enhan...
Ilie I. Luican, Hongwei Zhu, Florin Balasa