Sciweavers

3 search results - page 1 / 1
» A Methodology for Designing Efficient On-Chip Interconnects ...
Sort
View
HPCA
2003
IEEE
14 years 4 months ago
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
Wai Hong Ho, Timothy Mark Pinkston
DAC
2001
ACM
14 years 4 months ago
Latency-Driven Design of Multi-Purpose Systems-On-Chip
Milenko Drinic UCLA Computer Science Dep. 4732 Boelter Hall Los Angeles, CA 90095-1596 milenko@cs.ucla.edu Darko Kirovski Microsoft Research One Microsoft Way Redmond, WA 98052 da...
Seapahn Meguerdichian, Milenko Drinic, Darko Kirov...
JCP
2008
162views more  JCP 2008»
13 years 3 months ago
A Hypercube-based Scalable Interconnection Network for Massively Parallel Computing
An important issues in the design of interconnection networks for massively parallel computers is scalability. A new scalable interconnection network topology, called Double-Loop H...
Youyao Liu, Jungang Han, Huimin Du