37 search results - page 4 / 8 » A Modular Partitioning Approach for Asynchronous Circuit Syn... |
ACSD
2005
IEEE
13 years 11 months ago
2005
IEEE
Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
ACSD
2005
IEEE
13 years 11 months ago
2005
IEEE
Signal Transition Graphs (STGs) are a version of Petri nets for the specification of asynchronous circuit behaviour. It has been suggested to decompose such a specification as a...
EMSOFT
2005
Springer
13 years 11 months ago
2005
Springer
We consider the problem of synthesizing correct-by-construction globally asynchronous, locally synchronous (GALS) implementations from modular synchronous specifications. This in...
ISCAS
2007
IEEE
14 years 2 days ago
2007
IEEE
—A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of Functional Units has a great i...
DSD
2010
IEEE
13 years 3 months ago
2010
IEEE
Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementati...