27 search results - page 2 / 6 » A Multilevel Parallelization Framework for High-Order Stenci... |
EUROPAR
2006
Springer
13 years 8 months ago
2006
Springer
This paper presents the integration of a multi-level scheduler in the YML architecture. It demonstrates the advantages of this architecture based on a component model and why it is...
IPPS
2009
IEEE
13 years 11 months ago
2009
IEEE
Stencil computation (SC) is of critical importance for broad scientific and engineering applications. However, it is a challenge to optimize complex, highorder SC on emerging clus...
ICS
2009
Tsinghua U.
13 years 11 months ago
2009
Tsinghua U.
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
GCC
2004
Springer
13 years 10 months ago
2004
Springer
As an important aspect of grid security, access control model gets more and more attention. Entities in virtual organizations (VOs) must establish a dynamic, secure and cooperative...
IPPS
2002
IEEE
13 years 9 months ago
2002
IEEE
This paper presents preliminary efforts to develop compilation and execution environments that achieve performance portability of multilevel parallelization on hierarchical archit...