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» A Multithreaded Soft Processor for SoPC Area Reduction
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FCCM
2006
IEEE
125views VLSI» more  FCCM 2006»
13 years 10 months ago
A Multithreaded Soft Processor for SoPC Area Reduction
The growth in size and performance of Field Programmable Gate Arrays (FPGAs) has compelled System-on-aProgrammable-Chip (SoPC) designers to use soft processors for controlling sys...
Blair Fort, Davor Capalija, Zvonko G. Vranesic, St...
FPL
2007
Springer
121views Hardware» more  FPL 2007»
13 years 10 months ago
Improving Pipelined Soft Processors with Multithreading
Designers of FPGA-based systems are increasingly including soft processors—processors implemented in programmable logic—in their designs. Any combination of area, clock freque...
Martin Labrecque, J. Gregory Steffan
FCCM
2008
IEEE
114views VLSI» more  FCCM 2008»
13 years 10 months ago
Scaling Soft Processor Systems
As FPGA-based systems including soft-processors become increasingly common we are motivated to better understand the best way to scale the performance of such systems. In this pap...
Martin Labrecque, Peter Yiannacouras, J. Gregory S...
FPL
2009
Springer
135views Hardware» more  FPL 2009»
13 years 9 months ago
Fast critical sections via thread scheduling for FPGA-based multithreaded processors
As FPGA-based systems including soft processors become increasingly common, we are motivated to better understand the architectural trade-offs and improve the efficiency of these...
Martin Labrecque, J. Gregory Steffan
ICCD
2007
IEEE
205views Hardware» more  ICCD 2007»
14 years 1 months ago
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
David Meisner, Sherief Reda