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» A Network Memory Architecture Model and Performance Analysis
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ICS
2010
Tsinghua U.
13 years 9 months ago
Small-ruleset regular expression matching on GPGPUs: quantitative performance analysis and optimization
We explore the intersection between an emerging class of architectures and a prominent workload: GPGPUs (General-Purpose Graphics Processing Units) and regular expression matching...
Jamin Naghmouchi, Daniele Paolo Scarpazza, Mladen ...
AINA
2006
IEEE
13 years 11 months ago
Performance Analysis of Network Topologies in Agent-based Open Connectivity Architecture for DSS
Performance analysis of agent network topologies helps multi-agent system developers to understand the impact of topology on system efficiency and effectiveness. Appropriate topol...
Hao Lan Zhang, Clement H. C. Leung, Gitesh K. Raik...
DSN
2006
IEEE
13 years 11 months ago
Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures
—Multithreaded servers with cache-coherent shared memory are the dominant type of machines used to run critical network services and database management systems. To achieve the h...
Albert Meixner, Daniel J. Sorin
DATE
2003
IEEE
154views Hardware» more  DATE 2003»
13 years 10 months ago
Packetized On-Chip Interconnect Communication Analysis for MPSoC
Interconnect networks play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs. MPSoC performance and power consumption are greatly affected by the pac...
Terry Tao Ye, Luca Benini, Giovanni De Micheli
CASES
2003
ACM
13 years 10 months ago
Encryption overhead in embedded systems and sensor network nodes: modeling and analysis
Recent research in sensor networks has raised issues of security for small embedded devices. Security concerns are motivated by the deployment of a large number of sensory devices...
Ramnath Venugopalan, Prasanth Ganesan, Pushkin Ped...