Sciweavers

    1096 search results - page 220 / 220
    » A New Approach for Speeding Up Enumeration Algorithms
    Sort
    View
    ISPD
    2012
    ACM
    288views Hardware» more  ISPD 2012»
    Construction of realistic gate sizing benchmarks with known optimal solutions
    12 years 1 months ago
    Construction of realistic gate sizing benchmarks with known optimal solutions
    Download  vlsicad.ucsd.edu
    Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
    Andrew B. Kahng, Seokhyeong Kang
    claim paper
    Read More »
    Explore & Download
    Proceedings Preprints Top 5 Ranked Papers Publications Books Software Tutorials Presentations Lectures Notes Datasets
    Productivity Tools
    International On-screen Keyboard Graphical Social Symbols OCR Text Recognition CSS3 Style Generator Web Page to PDF Web Page to Image PDF Split PDF Merge Latex Equation Editor Sci2ools
    Document Tools
    PDF to Text PDF to Postscript PDF to Thumbnails Excel to PDF Word to PDF Postscript to PDF PowerPoint to PDF Latex to Word Repair Corrupted PDF
    Image Tools
    JPG to PS JPG to PDF Extract Images from PDF Image Converter
    Sciweavers
    About Community Cookies Privacy Policy Terms of Use

    Copyright © Sciweavers LLC, 2009-2024, USA.