16 search results - page 2 / 4 » A New Buffer Cache Design Exploiting Both Temporal and Conte... |
ASPLOS
2010
ACM
13 years 8 months ago
2010
ACM
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
MOBICOM
2010
ACM
13 years 5 months ago
2010
ACM
Localization is a fundamental operation for many wireless networks. While GPS is widely used for location determination, it is unavailable in many environments either due to its h...
LCTRTS
2005
Springer
13 years 11 months ago
2005
Springer
Effective use of the memory hierarchy is critical for achieving high performance on embedded systems. We focus on the class of streaming applications, which is increasingly preval...
FCCM
2009
IEEE
13 years 9 months ago
2009
IEEE
FPGA has long been considered an attractive platform for high performance implementations of string matching. However, as the size of pattern dictionaries continues to grow, such ...
HPCA
2004
IEEE
14 years 5 months ago
2004
IEEE
Recent research suggests that there are large variations in a cache's spatial usage, both within and across programs. Unfortunately, conventional caches typically employ fixe...