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ARITH
2003
IEEE
13 years 10 months ago
A New Iterative Structure for Hardware Division: The Parallel Paths Algorithm
This paper presents a new approach to hardware division—the parallel paths algorithm. In this approach, prescaling allows the division recurrence to be implemented by three proc...
Eric Rice, Richard Hughey
ASIACRYPT
2001
Springer
13 years 9 months ago
A Compact Rijndael Hardware Architecture with S-Box Optimization
Compact and high-speed hardware architectures and logic optimization methods for the AES algorithm Rijndael are described. Encryption and decryption data paths are combined and all...
Akashi Satoh, Sumio Morioka, Kohji Takano, Seiji M...
DATE
2010
IEEE
119views Hardware» more  DATE 2010»
13 years 10 months ago
Exploiting local logic structures to optimize multi-core SoC floorplanning
Abstract—We present a throughput-driven partitioning algorithm and a throughput-preserving merging algorithm for the high-level physical synthesis of latency-insensitive (LI) sys...
Cheng-Hong Li, Sampada Sonalkar, Luca P. Carloni
EUROPAR
2005
Springer
13 years 10 months ago
A Paradigm for Parallel Matrix Algorithms:
A style for programming problems from matrix algebra is developed with a familiar example and new tools, yielding high performance with a couple of surprising exceptions. The under...
David S. Wise, Craig Citro, Joshua Hursey, Fang Li...
VISUALIZATION
1996
IEEE
13 years 9 months ago
Real-Time Incremental Visualization of Dynamic Ultrasound Volumes Using Parallel BSP Trees
We present a method for producing real-time volume visualizations of continuously captured, arbitrarily-oriented 2D arrays (slices) of data. Our system constructs a 3D representat...
William F. Garrett, Henry Fuchs, Mary C. Whitton, ...