945 search results - page 1 / 189 » A New Method for Design of Robust Digital Circuits |
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
ISCAS
2007
IEEE
13 years 10 months ago
2007
IEEE
— Low-power consumption has become a highly important concern for synchronous standard-cell design, and consequently mandates the use of low-power design methodologies and techni...
DSD
2010
IEEE
13 years 4 months ago
2010
IEEE
Abstract—Continuously shrinking feature sizes cause an increasing vulnerability of digital circuits. Manufacturing failures and transient faults may tamper the functionality. Aut...
DATE
1999
IEEE
13 years 8 months ago
1999
IEEE
This paper presents a new Design for Testability (DFT) technique for Current-Mode Logic (CML) circuits. This new technique, with little overhead, using built-in detectors, monitor...
TVLSI
2002
13 years 4 months ago
2002
Gate diffusion input (GDI)--a new technique of low-power digital combinatorial circuit design--is described. This technique allows reducing power consumption, propagation delay, an...