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» A New Pipelined Array Architecture for Signed Multiplication
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FCCM
1998
IEEE
149views VLSI» more  FCCM 1998»
13 years 10 months ago
Configuration Compression for the Xilinx XC6200 FPGA
One of the major overheads in reconfigurable computing is the time it takes to reconfigure the devices in the system. This overhead limits the speedups possible in this exciting n...
Scott Hauck, Zhiyuan Li, Eric J. Schwabe
MICRO
2005
IEEE
105views Hardware» more  MICRO 2005»
13 years 11 months ago
Incremental Commit Groups for Non-Atomic Trace Processing
We introduce techniques to support efficient non-atomic execution of very long traces on a new binary translation based, x86-64 compatible VLIW microprocessor. Incrementally comm...
Matt T. Yourst, Kanad Ghose
SIGMOD
2011
ACM
176views Database» more  SIGMOD 2011»
12 years 8 months ago
Sharing work in keyword search over databases
An important means of allowing non-expert end-users to pose ad hoc queries — whether over single databases or data integration systems — is through keyword search. Given a set...
Marie Jacob, Zachary G. Ives
INFOCOM
2006
IEEE
13 years 11 months ago
Scheduling in Non-Blocking Buffered Three-Stage Switching Fabrics
— Three-stage non-blocking switching fabrics are the next step in scaling current crossbar switches to many hundreds or few thousands of ports. Congestion (output contention) man...
Nikolaos Chrysos, Manolis Katevenis
ACMMSP
2004
ACM
92views Hardware» more  ACMMSP 2004»
13 years 11 months ago
Instruction combining for coalescing memory accesses using global code motion
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...
Motohiro Kawahito, Hideaki Komatsu, Toshio Nakatan...