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» A New Pipelined Array Architecture for Signed Multiplication
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RTSS
2006
IEEE
13 years 11 months ago
Tightening the Bounds on Feasible Preemption Points
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
SIGGRAPH
1997
ACM
13 years 9 months ago
Rendering with coherent layers
For decades, animated cartoons and movie special effects have factored the rendering of a scene into layers that are updated independently and composed in the final display. We ap...
Jed Lengyel, John Snyder
ISCA
2000
IEEE
93views Hardware» more  ISCA 2000»
13 years 9 months ago
Reconfigurable caches and their application to media processing
High performance general-purpose processors are increasingly being used for a variety of application domains scienti c, engineering, databases, and more recently, media processing...
Parthasarathy Ranganathan, Sarita V. Adve, Norman ...