62 search results - page 1 / 13 » A Non-binary Parallel Arithmetic Architecture |
ICASSP
2011
IEEE
12 years 8 months ago
2011
IEEE
In this paper, based on the proposed parallelization scheme of binary arithmetic decoding, a parallel AVC/H.264 context-based adaptive binary arithmetic coding (CABAC) decoder wit...
CAP
2010
12 years 12 months ago
2010
In this work we study the feasibility of high-bandwidth, secure communications on generic machines equipped with the latest CPUs and General-Purpose Graphical Processing Units (GP...
IPPS
2000
IEEE
13 years 9 months ago
2000
IEEE
TEC
2002
13 years 4 months ago
2002
Abstract--In this paper, we present an efficient graph-based evolutionary optimization technique called evolutionary graph generation (EGG) and the proposed approach is applied to ...
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3...