522 search results - page 2 / 105 » A Note on Designing Logical Circuits Using SAT |
PPDP
2009
Springer
13 years 11 months ago
2009
Springer
This paper describes the encoding of a telecommunications feature subscription configuration problem to propositional logic and its solution using a state-of-the-art Boolean sati...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
SAT sweeping is a method for simplifying an AND/INVERTER graph (AIG) by systematically merging graph vertices from the inputs towards the outputs using a combination of structural...
ICCAD
2002
IEEE
14 years 2 months ago
2002
IEEE
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
DATE
1999
IEEE
13 years 9 months ago
1999
IEEE
The problem of checking the equivalence of combinational circuits is of key significance in the verification of digital circuits. In recent years, several approaches have been pro...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...