590 search results - page 1 / 118 » A Novel Method to Improve the Test Efficiency of VLSI Tests |
VLSID
2002
IEEE
14 years 4 months ago
2002
IEEE
This paper considers reducing the cost of test application by permuting test vectors to improve their defect coverage. Algorithms for test reordering are developed with the goal o...
DFT
2004
IEEE
13 years 8 months ago
2004
IEEE
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...
ISCAS
2008
IEEE
13 years 10 months ago
2008
IEEE
— Since the complexity of MIMO detection algorithms is exponential, the K–best algorithm is often chosen for efficient VLSI implementation. This detection problem is often view...
TVLSI
2010
12 years 11 months ago
2010
Abstract--Higher circuit densities in system-on-chip (SOC) designs have led to drastic increase in test data volume. Larger test data size demands not only higher memory requiremen...
VLSID
2001
IEEE
14 years 4 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...