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» A Novel Superscalar Architecture for Fast DCT Implementation
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CHES
2009
Springer
162views Cryptology» more  CHES 2009»
14 years 6 months ago
Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers
Abstract. This paper is devoted to the design of fast parallel accelerators for the cryptographic Tate pairing in characteristic three over supersingular elliptic curves. We propos...
Jean-Luc Beuchat, Jérémie Detrey, Ni...
SIGMOD
2004
ACM
157views Database» more  SIGMOD 2004»
14 years 6 months ago
Holistic UDAFs at streaming speeds
Many algorithms have been proposed to approximate holistic aggregates, such as quantiles and heavy hitters, over data streams. However, little work has been done to explore what t...
Graham Cormode, Theodore Johnson, Flip Korn, S. Mu...
ICCD
2008
IEEE
111views Hardware» more  ICCD 2008»
14 years 3 months ago
Power switch characterization for fine-grained dynamic voltage scaling
—Dynamic voltage scaling (DVS) provides power savings for systems with varying performance requirements. One low overhead implementation of DVS uses PMOS power switches to connec...
Liang Di, Mateja Putic, John Lach, Benton H. Calho...
SOSE
2008
IEEE
14 years 12 days ago
A Sustainable Service-Oriented B2C Framework for Small Businesses
Electronic commerce is fast expanding all over the world. Currently most B2C (Business to Customer) electronic commerce focuses on retailing and other online services, such as onl...
Xiaodong Liu, Hailiang Ye
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
13 years 10 months ago
Hardware Synthesis from C/C++ Models
Software programming languages, such as C/C++, have been used as means for specifying hardware for quite a while. Different design methodologies have exploited the advantages of f...
Giovanni De Micheli