3 search results - page 1 / 1 » A Parallel Architecture for Hermitian Decoders: Satisfying R... |
ISCAS
2007
IEEE
13 years 10 months ago
2007
IEEE
— Hermitian Codes offer desirable properties such as large code lengths, good error-correction at high code rates, etc. The main problem in making Hermitian codes practical is to...
SIPS
2006
IEEE
13 years 10 months ago
2006
IEEE
Abstract— In this paper, we propose partly parallel architectures based on optimal overlapped sum-product (OSP) decoding. To ensure high throughput and hardware utilization effi...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
In designing bus based systems with parallel and pipelined architecture, it is important to derive a real time budget (a specified execution time limit) for each task of a bus bas...