7 search results - page 2 / 2 » A Parallel for Loop Memory Template for a High Level Synthes... |
IPPS
1999
IEEE
13 years 9 months ago
1999
IEEE
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
CGO
2008
IEEE
13 years 11 months ago
2008
IEEE
The recent trend in the processor industry of packing multiple processor cores in a chip has increased the importance of automatic techniques for extracting thread level paralleli...