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» A Performance Comparison of Tree and Ring Topologies in Dist...
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DATE
2006
IEEE
100views Hardware» more  DATE 2006»
13 years 10 months ago
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
Luciano Bononi, Nicola Concer
ASPDAC
2011
ACM
217views Hardware» more  ASPDAC 2011»
12 years 8 months ago
Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core syst
This paper studies realization and performance comparison of the sequential and weak consistency models in the network-on-chip (NoC) based distributed shared memory (DSM) multi-cor...
Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jants...
DATE
2003
IEEE
103views Hardware» more  DATE 2003»
13 years 9 months ago
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
Dimitrios Velenis, Marios C. Papaefthymiou, Eby G....
PODC
2009
ACM
14 years 5 months ago
Brief announcement: minimum spanning trees and cone-based topology control
Consider a setting where nodes can vary their transmission power thereby changing the network topology, the goal of topology control is to reduce the transmission power while ensu...
Alejandro Cornejo, Nancy A. Lynch
IAJIT
2011
12 years 8 months ago
The chained-cubic tree interconnection network
: The core of a parallel processing system is the interconnection network by which the system’s processors are linked. Due to the great role played by the interconnection network...
Malak Abdullah, Emad Abuelrub, Basel Mahafzah