239 search results - page 46 / 48 » A Performance Evaluation of the Convex SPP-1000 Scalable Sha... |
HPCA
2011
IEEE
12 years 9 months ago
2011
IEEE
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...
CLUSTER
2006
IEEE
13 years 12 months ago
2006
IEEE
This paper presents a middleware framework for storing, accessing and analyzing massive-scale semantic graphs. The framework, MSSG, targets scale-free semantic graphs with O(1012 ...
EMSOFT
2005
Springer
13 years 11 months ago
2005
Springer
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...
HIPC
2005
Springer
13 years 11 months ago
2005
Springer
Abstract. The proliferation of multiprocessor servers and multithreaded applications has increased the demand for high-performance synchronization. Traditional scheduler-based lock...
MICRO
2003
IEEE
13 years 11 months ago
2003
IEEE
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...