22 search results - page 4 / 5 » A Performance Evaluation of the Nehalem Quad-Core Processor ... |
HPCA
2007
IEEE
14 years 6 months ago
2007
IEEE
Transactional Memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, pr...
CF
2004
ACM
13 years 9 months ago
2004
ACM
Off-chip memory accesses are a major source of power consumption in embedded processors. In order to reduce the amount of traffic between the processor and the off-chip memory as ...
HPCA
2008
IEEE
14 years 6 months ago
2008
IEEE
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
TC
2008
13 years 5 months ago
2008
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
HPDC
2008
IEEE
14 years 6 days ago
2008
IEEE
Today Graphics Processing Units (GPUs) are a largely underexploited resource on existing desktops and a possible costeffective enhancement to high-performance systems. To date, mo...