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» A Petri Net Model for Evaluating Packet Buffering Strategies...
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QEST
2007
IEEE
12 years 26 days ago
A Petri Net Model for Evaluating Packet Buffering Strategies in a Network Processor
Previous studies have shown that buffering packets in DRAM is a performance bottleneck. In order to understand the impediments in accessing the DRAM, we developed a detailed Petri...
Girish B. C., R. Govindarajan
IPPS
2007
IEEE
12 years 27 days ago
Packet Reordering in Network Processors
Network processors today consists of multiple parallel processors (microengines) with support for multiple threads to exploit packet level parallelism inherent in network workload...
S. Govind, R. Govindarajan, Joy Kuri
SAMOS
2005
Springer
12 years 2 days ago
Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets
The design of appropriate communication architectures for complex Systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Chi...
Holger Blume, Thorsten von Sydow, Daniel Becker, T...
JSA
2007
123views more  JSA 2007»
11 years 6 months ago
Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures
The design of appropriate communication architectures for complex Systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Ch...
Holger Blume, Thorsten von Sydow, Daniel Becker, T...
AINA
2008
IEEE
12 years 1 months ago
Thread Allocation in Chip Multiprocessor Based Multithreaded Network Processors
—This work tries to derive ideas for thread allocation in Chip Multiprocessor (CMP)-based network processors performing general applications by Continuous-Time Markov Chain model...
Yi-Neng Lin, Ying-Dar Lin, Yuan-Cheng Lai
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