64 search results - page 1 / 13 » A Polynomial Time Approximation Scheme for Minimum Routing C... |
SODA
1998
ACM
13 years 5 months ago
1998
ACM
Given an undirected graph with nonnegative costs on the edges, the routing cost of any of its spanning trees is the sum over all pairs of vertices of the cost of the path between t...
DAC
2009
ACM
14 years 5 months ago
2009
ACM
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
ISPD
2009
ACM
13 years 11 months ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
PDCAT
2005
Springer
13 years 10 months ago
2005
Springer
We consider the practical NP-complete problem of finding a minimum weight spanning tree with both edge weights and inner nodes weights. We present two polynomial time algorithms ...