33 search results - page 1 / 7 » A Power Minimization Technique for Arithmetic Circuits by Ce... |
VLSID
2002
IEEE
14 years 4 months ago
2002
IEEE
As a basic cell of arithmetic circuits, a one-bit full adder and a counter are usually used. Minimizing power consumption of these components is a key issue for low-power circuit ...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
Designs which do not fully utilize their arithmetic datapath components typically exhibit a significant overhead in power consumption. Whenever a module performs an operation who...
ISMVL
2010
IEEE
13 years 9 months ago
2010
IEEE
—Fixed-point multiplication architectures are designed and evaluated using a set of logic cells based on a radix-4, quaternary number system. The library of logic circuits is bas...
ARITH
2009
IEEE
13 years 11 months ago
2009
IEEE
Datapath synthesis for standard-cell design goes through extraction of arithmetic operations from RTL code, high-level arithmetic optimizations and netlist generation. Numerous ar...
ISVLSI
2003
IEEE
13 years 9 months ago
2003
IEEE
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random...