Sciweavers

35 search results - page 1 / 7
» A Proposal for Transaction-Level Verification with Component...
Sort
View
DATE
2003
IEEE
87views Hardware» more  DATE 2003»
13 years 9 months ago
A Proposal for Transaction-Level Verification with Component Wrapper Language
We propose a new approach to accelerate transaction level verification by raising the productivity of the verification suites including test patterns, protocol checker, and simula...
Koji Ara, Kei Suzuki
ECOOP
2000
Springer
13 years 8 months ago
Generic Wrappers
Abstract. Component software means reuse and separate marketing of pre-manufactured binary components. This requires components from different vendors to be composed very late, pos...
Martin Büchi, Wolfgang Weck
ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
13 years 10 months ago
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
— This paper presents an architecture and a wrapper synthesis approach for the design of multi-clock systems-on-chips. We build upon the initial work on multi-clock latency-insen...
Ankur Agiwal, Montek Singh
OOPSLA
2010
Springer
13 years 2 months ago
Component adaptation and assembly using interface relations
Software’s expense owes partly to frequent reimplementation of similar functionality and partly to maintenance of patches, ports or components targeting evolving interfaces. Mor...
Stephen Kell
FDL
2007
IEEE
13 years 10 months ago
Modelling Alternatives for Cycle Approximate Bus TLMs
Transaction level models (TLMs) can be constructed at t levels of abstraction, denoted as untimed (UT), cycle-approximate (CX), and cycle accurate (CA) in this paper. The choice o...
Martin Radetzki, Rauf Salimi Khaligh