4 search results - page 1 / 1 » A Quadruple Precision and Dual Double Precision Floating-Poi... |
DSD
2003
IEEE
13 years 10 months ago
2003
IEEE
Double precision floating-point arithmetic is inadequate for many scientific computations. This paper presents the design of a quadruple precision floating-point multiplier tha...
CDES
2006
13 years 6 months ago
2006
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
ISPDC
2010
IEEE
13 years 3 months ago
2010
IEEE
—With systems such as Road Runner, there is a trend in super computing to offload parallel tasks to special purpose co-processors, composed of many relatively simple scalar proc...
ARITH
2009
IEEE
13 years 11 months ago
2009
IEEE
We introduce a novel left-to-right leading digit first dual recoding of an operand for the purpose of designing the squaring operation on that operand. Our dual recoding yields an...