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» A RISC Processor with Extended Forwarding
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ARCS
1997
Springer
13 years 9 months ago
A RISC Processor with Extended Forwarding
The paper examines a simple conceptual modification of the operation unit of a RISC processor. We propose to substitute a part of the conventional general purpose register file by...
Gert Markwardt, Günter Kemnitz, Rainer G. Spa...
ISCAS
2007
IEEE
101views Hardware» more  ISCAS 2007»
13 years 11 months ago
Flexible and Cost Effective Transport Stream Processor for DTV
— A flexible transport stream processor for DTV which is also designed under cost-effective consideration is proposed in this paper. A RISC micro-controller is allocated as the ...
Chia-Liang Tsai, Shao-Yi Chien
DAC
2001
ACM
14 years 5 months ago
Automated Pipeline Design
The interlock and forwarding logic is considered the tricky part of a fully-featured pipelined microprocessor and especially debugging these parts delays the hardware design proce...
Daniel Kroening, Wolfgang J. Paul
MICRO
1993
IEEE
127views Hardware» more  MICRO 1993»
13 years 9 months ago
An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors
The conventional classification of inter-instruction dependencies (data, anti and output dependencies) provides a basic scheme for the analysis of pipeline hazards in pipelined in...
Ing-Jer Huang, Alvin M. Despain
DATE
2010
IEEE
146views Hardware» more  DATE 2010»
13 years 5 months ago
Automatic pipelining from transactional datapath specifications
Abstract—We present a transactional datapath specification (Tspec) and the tool (T-piper) to synthesize automatically an inpelined implementation from it. T-spec abstractly views...
Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-...