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HPCA
2005
IEEE
14 years 4 months ago
A Small, Fast and Low-Power Register File by Bit-Partitioning
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
Masaaki Kondo, Hiroshi Nakamura
ASPDAC
2008
ACM
69views Hardware» more  ASPDAC 2008»
13 years 6 months ago
Fast, quasi-optimal, and pipelined instruction-set extensions
Nowadays many customised embedded processors offer the possibility of speeding up an application by implementing it using Application-Specific Functional units (AFUs). However, th...
Ajay K. Verma, Philip Brisk, Paolo Ienne
MICRO
2003
IEEE
143views Hardware» more  MICRO 2003»
13 years 9 months ago
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power
Energy-efficient processor design is becoming more and more important with technology scaling and with high performance requirements. Supply-voltage scaling is an efficient way to...
Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik ...
ISCA
2011
IEEE
271views Hardware» more  ISCA 2011»
12 years 8 months ago
CRIB: consolidated rename, issue, and bypass
Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined exec...
Erika Gunadi, Mikko H. Lipasti
ICCD
2006
IEEE
138views Hardware» more  ICCD 2006»
14 years 1 months ago
Delay and Area Efficient First-level Cache Soft Error Detection and Correction
—Soft error rates are an increasing problem in modern VLSI circuits. Commonly used error correcting codes reduce soft error rates in large memories and second level caches but ar...
Karl Mohr, Lawrence Clark