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EUROPAR
2007
Springer
13 years 11 months ago
Hardware Transactional Memory with Operating System Support, HTMOS
Abstract. Hardware Transactional Memory (HTM) gives software developers the opportunity to write parallel programs more easily compared to any previous programming method, and yiel...
Sasa Tomic, Adrián Cristal, Osman S. Unsal,...
HASE
2007
IEEE
13 years 11 months ago
Systems Architectures for Transactional Network Interface
Systems such as software transactional memory and some exception handling techniques use transactions. However, a typical limitation of such systems is that they do not allow syst...
Manish Marwah, Shivakant Mishra, Christof Fetzer
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
11 years 7 months ago
BlockChop: Dynamic squash elimination for hybrid processor architecture
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
Jason Mars, Naveen Kumar
ISLPED
2010
ACM
158views Hardware» more  ISLPED 2010»
13 years 3 months ago
STM versus lock-based systems: an energy consumption perspective
The shift towards multicore processors and the well-known drawbacks imposed by lock-based synchronization have forced researchers to devise new alternatives for building concurren...
Felipe Klein, Alexandro Baldassin, Joao Moreira, P...
PPOPP
2006
ACM
13 years 11 months ago
McRT-STM: a high performance software transactional memory system for a multi-core runtime
Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed t...
Bratin Saha, Ali-Reza Adl-Tabatabai, Richard L. Hu...