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ICCAD
2003
IEEE
379views Hardware» more  ICCAD 2003»
14 years 16 days ago
A Statistical Gate-Delay Model Considering Intra-Gate Variability
This paper proposes a model for calculating statistical gate-delay variation caused by intra-chip and inter-chip variability. As the variation of individual gate delays directly i...
Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera
DAC
2004
ACM
13 years 7 months ago
Statistical gate delay model considering multiple input switching
There is an increased dominance of intra-die process variations, creating a need for an accurate and fast statistical timing analysis. Most of the recent proposed approaches assum...
Aseem Agarwal, Florentin Dartu, David Blaauw
ASPDAC
2008
ACM
169views Hardware» more  ASPDAC 2008»
13 years 5 months ago
Analytical model for the impact of multiple input switching noise on timing
The timing models used in current Static Timing Analysis tools use gate delays only for single input switching events. It is well known that the temporal proximity of signals arriv...
Rajeshwary Tayade, Sani R. Nassif, Jacob A. Abraha...
DAC
2005
ACM
13 years 5 months ago
Mapping statistical process variations toward circuit performance variability: an analytical modeling approach
A physical yet compact gate delay model is developed integrating short-channel effects and the Alpha-power law based timing model. This analytical approach accurately predicts bot...
Yu Cao, Lawrence T. Clark
DATE
2006
IEEE
158views Hardware» more  DATE 2006»
13 years 9 months ago
Modeling multiple input switching of CMOS gates in DSM technology using HDMR
Abstract— Continuing scaling of CMOS technology has allowed aggressive pursuant of increased clock rate in DSM chips. The ever shorter clock period has made switching times of di...
Jayashree Sridharan, Tom Chen