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FPL
2006
Springer
103views Hardware» more  FPL 2006»
13 years 8 months ago
A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification
This paper provides a realistic case study of using the previously introduced SIMPPL system architectural model, which fixes the physical interface and communication protocols bet...
Lesley Shannon, Blair Fort, Samir Parikh, Arun Pat...
VLSID
2003
IEEE
180views VLSI» more  VLSID 2003»
14 years 4 months ago
Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
Pao-Ann Hsiung, Shu-Yu Cheng
HASE
2008
IEEE
13 years 4 months ago
Aiding Modular Design and Verification of Safety-Critical Time-Triggered Systems by Use of Executable Formal Specifications
Designing safety-critical systems is a complex process, and especially when the design is carried out at different f abstraction where the correctness of the design at one level i...
Kohei Sakurai, Péter Bokor, Neeraj Suri
ISQED
2005
IEEE
116views Hardware» more  ISQED 2005»
13 years 10 months ago
A Mask Reuse Methodology for Reducing System-on-a-Chip Cost
Today's System-on-a-Chip (SoC) design methodology provides an efficient way to develop highly integrated systems on a single chip by utilizing pre-designed intellectual prope...
Subhrajit Bhattacharya, John A. Darringer, Daniel ...
DAC
1996
ACM
13 years 8 months ago
Integrating Formal Verification Methods with A Conventional Project Design Flow
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
Ásgeir Th. Eiríksson