294 search results - page 4 / 59 » A System Level Resource Estimation Tool for FPGAs |
DATE
2002
IEEE
14 years 3 months ago
2002
IEEE
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic de...
ICCAD
2001
IEEE
14 years 7 months ago
2001
IEEE
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
ESCIENCE
2006
IEEE
14 years 4 months ago
2006
IEEE
An important factor that needs to be taken into account by end-users and systems (schedulers, resource brokers, policy brokers) when mapping applications to the Grid, is the perfo...
FPL
2000
Springer
14 years 2 months ago
2000
Springer
As integration levels in FPGA devices have increased over the past decade, the structure of programmable logic resources has become more diversified. Recently, Altera Corporation h...
FPGA
1998
ACM
14 years 3 months ago
1998
ACM
In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA...