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» A Systematic Approach for Diagnosing Multiple Delay Faults
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DSS
2008
102views more  DSS 2008»
13 years 5 months ago
Diagnosing decision quality
Human decision making is error-prone and often subject to biases. Important information cues are misweighted and feedback delays hamper learning. Experimentally, task information ...
Michael J. Davern, Ravi Mantena, Edward A. Stohr
ET
2010
98views more  ET 2010»
13 years 3 months ago
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...
Stephan Eggersglüß, Görschwin Fey,...
ASPDAC
2004
ACM
112views Hardware» more  ASPDAC 2004»
13 years 10 months ago
Longest path selection for delay test under process variation
- Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay...
Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, We...
DSN
2007
IEEE
13 years 11 months ago
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...
DAC
2006
ACM
13 years 7 months ago
Systematic software-based self-test for pipelined processors
Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving ...
Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis H...