106 search results - page 4 / 22 » A Task-Centric Memory Model for Scalable Accelerator Archite... |
IISWC
2008
IEEE
14 years 5 days ago
2008
IEEE
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, handcoded microbenchmarks can be used to accelerate performance e...
CVPR
2011
IEEE
12 years 11 months ago
2011
IEEE
We propose a reduced algebraic cost based on pairwise epipolar constraints for the iterative refinement of a multiple view 3D reconstruction. The aim is to accelerate the intermedi...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of ...
ICPP
2008
IEEE
14 years 6 days ago
2008
IEEE
—We address the recently recognized privatization problem in software transactional memory (STM) runtimes, and introduce the notion of partially visible reads (PVRs) to heuristic...
ASPLOS
2008
ACM
13 years 7 months ago
2008
ACM
Nested paging is a hardware solution for alleviating the software memory management overhead imposed by system virtualization. Nested paging complements existing page walk hardwar...