10 search results - page 1 / 2 » A Timestamp-based Selective Invalidation Scheme for Multipro... |
ICPP
1996
IEEE
13 years 8 months ago
1996
IEEE
- Among all software cache coherence strategaes, the ones that are based on the concept of tamestamps show the greatest potentaal an terms of cache performance. The early tamestamp...
ICPADS
1994
IEEE
13 years 8 months ago
1994
IEEE
: Software cache coherence schemes are very desirable in the design of scalable multiprocessors and massively parallel processors. The authors propose a software cache coherence sc...
TC
2011
12 years 11 months ago
2011
— Implementing shared memory consistency models on top of hardware caches gives rise to the well-known cache coherence problem. The standard solution involves implementing cohere...
ISCA
1995
IEEE
13 years 8 months ago
1995
IEEE
This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation messages...
ICPP
2009
IEEE
13 years 2 months ago
2009
IEEE
This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this c...