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ISCA
1995
IEEE
98views Hardware» more  ISCA 1995»
13 years 9 months ago
Instruction Fetching: Coping with Code Bloat
Previous research has shown that the SPEC benchmarks achieve low miss ratios in relatively small instruction caches. This paper presents evidence that current software-development...
Richard Uhlig, David Nagle, Trevor N. Mudge, Stuar...
JUCS
2000
120views more  JUCS 2000»
13 years 5 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
CN
2004
95views more  CN 2004»
13 years 5 months ago
Distinguishing between single and multi-source attacks using signal processing
Launching a denial of service (DoS) attack is trivial, but detection and response is a painfully slow and often a manual process. Automatic classification of attacks as single- or...
Alefiya Hussain, John S. Heidemann, Christos Papad...
SIGCOMM
2003
ACM
13 years 11 months ago
A framework for classifying denial of service attacks
Launching a denial of service (DoS) attack is trivial, but detection and response is a painfully slow and often a manual process. Automatic classification of attacks as single- o...
Alefiya Hussain, John S. Heidemann, Christos Papad...
SAMOS
2004
Springer
13 years 11 months ago
High-Level Energy Estimation for ARM-Based SOCs
In recent years, power consumption has become a critical concern for many VLSI systems. Whereas several case studies demonstrate that technology-, layout-, and gate-level technique...
Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, P...